1. Field of the Invention
This invention relates to a computer system, a bus interface unit, and a tag register within system memory of the computer for enlarging the number of a direct memory access ("DMA") transfers within a chain of DMA transfers which can be kept track of without enlarging a tag register within the bus interface unit or, more particularly, within a DMA controller of the bus interface unit.
2. Description of the Related Art
A time-consuming activity of a microprocessor entails moving blocks of memory from one subsystem within a computer system to another subsystem. The memory-moving chores can, in some instances, be handled by a DMA controller.
A DMA controller may include a specialized processor and numerous registers which keep track of the base location or source from which bytes of data are to be moved, the address or destination to where those bytes should be placed, and the number of bytes involved in the move operation. By noting the source, destination, and general operating parameters of the DMA transfer, the DMA controller allows direct communication from a peripheral device to system memory, or directly between peripheral devices (i.e., devices connected to a peripheral bus within the computer system). The DMA controller thereby provides communication without intervention of the host processor.
The mechanism by which the DMA controller provides a channel between the peripheral device and the system memory occurs in accordance with a channel program or control blocks programmed within the system memory. Control blocks contain fields which are programmed with values that, when fetched by the DMA controller, instructs the DMA controller to transfer the desired data to or from system memory. In addition to having a transfer control field, each control block may also contain a field which denotes a specific buffer within the DMA controller. That buffer will then be used to receive data transferred to or from a peripheral device (depending on whether the transfer operation is a read request or write request cycle).
The control blocks are essentially storage locations within the system memory, and may be partially programmed during boot-up of the computer system. An important advantage in using control blocks is that one control block can point to a successive control block, and so forth to form a "chain" of control blocks. Therefore, each control block is used to control a single DMA transfer of data, and by linking numerous control blocks together in a chain, a sequence of DMA transfers can occur without host processor intervention. Thus, in addition to the transfer field and the buffer pointer field, each control block may also have a pointer field directed to the next control block within the sequence. A description of control blocks, and control block chaining, is set forth in further detail within, for example, U.S. Pat. No. 5,251,312 (herein incorporated by reference).
The number of control blocks that can be chained together is limited by the amount of memory allocated to the DMA controller. If sufficient space is properly allocated, a rather large sequence of DMA transfers can be controlled by the chain of control blocks. The transfer sequence will continue until data attributed to the entire chain has been transferred, if an error is detected and acknowledged by the DMA controller, or when the program wants indication of the current quantity of data DMA-transferred. A tag field within a hardware tag register of the DMA controller serves to denote which particular block was being processed within the chain when the interrupt occurred. The interrupt may have been intentional, in that a software program (operating system or application program) might be set to indicate when the DMA controller had transferred a certain quantity of data. Alternatively, the interrupt may have been unintentional by virtue of the interrupt signaling that an error in processing occurred. More specifically, each control block contains a unique tag field value. That value is forwarded within the respective control block within the chain as the chain of control blocks are being processed. When the DMA controller induces either an unintentional or intentional interrupt, the tag value of the currently fetched or "processed" control block is recorded in the controller's hardware tag register. Once the interrupt has been serviced, the DMA transfers can then be resumed, or the entire transfer aborted. Beneficially, however, the DMA transfers begin with control blocks immediately succeeding the control block which has its tag value stored in the hardware tag register. In this manner, DMA transfers can be quickly resumed at the point in which the interrupt occurs.
Many DMA controllers available in the marketplace have a tag field, and a fixed number of bits within the hardware tag register. However, the number of control blocks within a chain is variable, and there may be instances in which the number of chained control blocks can exceed those fixed number of bits. Merely as an example, conventional DMA controllers may reserve only four bits to the hardware tag register. If the chain is to exceed 2.sup.4, or 16 control blocks, then not all control blocks can be uniquely identified such that a control block immediately succeeding an interrupt can be directly resumed after an error has been solved. In this instance, processing the chain after interrupt must resume at the first control block within the chain, even though possibly one-half or more of the chain have been processed prior to the interrupt. Having to proceed with earlier-processed control blocks subsequent to interrupt, imposes a significant performance penalty upon the memory bus and thereby limits the overall benefit of chaining.
It would be desirable to introduce a mechanism for keeping track of a larger number of control blocks, and the position of a control block within a rather large chain during an interrupt. It would be further beneficial to implement the mechanism without having to change the fixed number of bits within the hardware tag register, or having to change any hardware component within the DMA controller itself. The desirous mechanism is therefore one which can modify and enhance many existing DMA controller currently available in the marketplace for the benefit of accommodating a rather large and variable length chain of control blocks.